1/8 march 2003 STE70NM60 n-channel 600v - 0.050 w - 70a isotop zener-protected mdmesh?power mosfet typical r ds (on) = 0.050 w high dv/dt and avalanche capabilities improved esd capability low input capacitance and gate charge low gate input resistance tight process control industrys lowest on-resistance description the mdmesh? is a new revolutionary mosfet technology that associates the multiple drain pro- cess with the companys powermesh? horizontal layout. the resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. the adoption of the companys proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competitions products. applications the mdmesh? family is very suitable for increasing power density of high voltage converters allowing system miniaturization and higher efficiencies. ordering information type v dss r ds(on) i d STE70NM60 600v < 0.055 w 70 a sales type marking package packaging STE70NM60 e70nm60 isotop tube isotop internal schematic diagram
STE70NM60 2/8 absolute maximum ratings (?)pulse width limited by safe operating area (1) i sd 70a, di/dt 400 a/s, v dd v (br)dss ,t j t jmax. thermal data avalanche characteristics gate-source zener diode protection features of gate-to-source zener diodes the built-in back-to-back zener diodes have specifically been designed to enhance not only the devices esd capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. in this respect the zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the devices integrity. these integrated zener diodes thus avoid the usage of external components. symbol parameter value unit v ds drain-source voltage (v gs =0) 600 v v dgr drain-gate voltage (r gs =20k w ) 600 v v gs gate- source voltage 30 v i d drain current (continuous) at t c = 25c 70 a i d drain current (continuous) at t c = 100c 44 a i dm ( ) drain current (pulsed) 280 a p tot total dissipation at t c = 25c 600 w v esd(g-s) gate source esd(hbm-c=100pf, r=15k w) 6kv derating factor 4.5 w/c dv/dt (1) peak diode recovery voltage slope 15 v/ns t stg storage temperature C65 to 150 c t j max. operating junction temperature 150 c rthj-case thermal resistance junction-case max 0.2 c/w rthj-amb thermal resistance junction-ambient max 30 c/w t l maximum lead temperature for soldering purpose 300 c symbol parameter max value unit i ar avalanche current, repetitive or not-repetitive (pulse width limited by t j max) 30 a e as single pulse avalanche energy (starting t j = 25 c, i d =i ar ,v dd =35v) 1.4 j symbol parameter test conditions min. typ. max. unit bv gso gate-source breakdown voltage igs= 1ma (open drain) 30 v
3/8 STE70NM60 electrical characteristics (t case = 25 c unless otherwise specified) on/off dynamic switching on switching off source drain diode note: 1. pulsed: pulse duration = 300 s, duty cycle 1.5 %. 2. pulse width limited by safe operating area. symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 600 v i dss zero gate voltage drain current (v gs =0) v ds = max rating 10 a v ds = max rating, t c = 125c 100 a i gss gate-body leakage current (v ds =0) v gs = 20v 10 a v gs(th) gate threshold voltage v ds =v gs ,i d = 250 a 34 5v r ds(on) static drain-source on resistance v gs =10v,i d = 30 a 0.050 0.055 w symbol parameter test conditions min. typ. max. unit g fs (1) forward transconductance v ds =i d(on) xr ds(on)max, i d =30a 35 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds =25v,f=1mhz,v gs = 0 7300 2000 40 pf pf pf r g gate input resistance f=1 mhz gate dc bias = 0 test signal level = 20mv open drain 1.8 w symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on delay time rise time v dd =300v,i d =30a r g = 4.7 w v gs =10v (see test circuit, figure 3) 55 95 ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd =470v,i d =60a, v gs =10v 178 44.5 95 266 nc nc nc symbol parameter test conditions min. typ. max. unit t r(voff) t f t c off-voltage rise time fall time cross-over time v dd = 400 v, i d =60a, r g =4.7 w, v gs =10v (see test circuit, figure 5) 130 76 105 ns ns ns symbol parameter test conditions min. typ. max. unit i sd i sdm (2) source-drain current source-drain current (pulsed) 60 240 a a v sd (1) forward on voltage i sd =60a,v gs =0 1.5 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 60 a, di/dt = 100 a/s, v dd =30v,t j = 150c (see test circuit, figure 5) 600 14 48 ns c a
STE70NM60 4/8 safe operating area thermal impedance transconductance transfer characteristics output characteristics static drain-source on resistance
5/8 STE70NM60 capacitance variations gate charge vs gate-source voltage normalized bvdss vs temperature normalized on resistance vs temperature source-drain diode forward characteristics normalized gate threshold voltage vs temp.
STE70NM60 6/8 fig. 5: test circuit for inductive load switching and diode recovery times fig. 4: gate charge test circuit fig. 2: unclamped inductive waveform fig. 1: unclamped inductive load test circuit fig. 3: switching times test circuit for resistive load
7/8 STE70NM60 dim. mm inch min. typ. max. min. typ. max. a 11.8 12.2 0.466 0.480 b 8.9 9.1 0.350 0.358 c 1.95 2.05 0.076 0.080 d 0.75 0.85 0.029 0.033 e 12.6 12.8 0.496 0.503 f 25.15 25.5 0.990 1.003 g 31.5 31.7 1.240 1.248 h4 0.157 j 4.1 4.3 0.161 0.169 k 14.9 15.1 0.586 0.594 l 30.1 30.3 1.185 1.193 m 37.8 38.2 1.488 1.503 n4 0.157 o 7.8 8.2 0.307 0.322 b e h o n j k l m f a c g d isotop mechanical data
STE70NM60 8/8 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com
|
